Phase-locked loops (PLL's) are widely-used circuits. PLL's have traditionally been used to generate clock signals of desired frequencies from an input reference clock. Some PLL's have employed a second loop to further aid in locking, stabilizing, or quickly acquiring the clock frequency at initialization. See for example U.S. Pat. No. 5,329,250 by Imaizumi et al., assigned to Sanyo Electric Co., and U.S. Pat. No. 5,113,152 by Norimatsu, assigned to NEC Corp. Imaizumi uses two PLL loops, each with their own voltage-controlled oscillator (VCO), while Norimatsu uses a variable loop filter.
A more recent application of PLL's is for generating a modulated clock rather than a stable clock. A slow modulation is intentionally introduced into the output clock. This modulation of the clock's frequency is known as spread spectrum. Two VCO's are used by Hardin in U.S. Pat. No. 5,631,920, assigned to Lexmark International, Inc. Bland in U.S. Pat. No. 5,610,955, assigned to Microclock Inc. of San Jose, Calif., uses a single loop, but with a variable divider in the feedback path.
EMI Interference
Electronic equipment can often generate interference that creates disturbances in other electronic equipment. For example, a portable computer may emit radiation that interferes with a television receiver. Intentional receivers, such as televisions, cellular phones, pagers, and wireless devices, are often affected by unintentional transmitters that emit electromagnetic radiation. As both types of electronic equipment become more common, interference becomes more noticeable to the consumer.
Electromagnetic interference (EMI) is a measure of the amount of interference that an electronic device (the unintentional transmitter) disturbs an intentional receiver. Government agencies such as the Federal Communication Commission (FCC) strictly regulate the amount of radiation or EMI that an electronic device can generate.
Portable devices such as portable personal computers (PC's) are particularly problematic since these portable devices are easily placed near televisions or other receivers. Cramped office and living spaces often force electronic equipment closer together. Since radiation rapidly increases with smaller distances, smaller and more portable equipment often appear to generate more interference.
Improving technology also worsens the EMI problem. Faster clock rates of higher-speed PC's generate more radiation. Higher resolution monitors and displays require that more pixels be transferred to the screen for each screen refresh period; thus a higher clock rate and more interference results.
Traditional techniques to reduce EMI attempt to contain radiation or to reduce the amount of radiation generated. Coax wires and shielded cables are effective at containing radiation, but are expensive, heavy, bulky, and inflexible. The weight and bulk of shielded cables make them undesirable for portable computers. The bulk and relative inflexibility of shielded cables makes it difficult to thread them through the clam-shell hinges connecting the graphics controller in the keyboard-containing base unit with the flat-panel display. Metal chassis with sealed seams are effective for reducing EMI of desktop PC's, but portable PC's are kept light by using plastic. Toxic metal paints are sometimes sprayed on plastic housings for portable PC's to provide shielding.
Lower voltages reduce the intensity of the radiation generated, and the new 3-volt standard has helped reduce EMI at all harmonics. Proper impedance matching and termination of signals reduces ringing and harmonics, and shorter signal traces further reduce radiation. Ground planes on PCB's or ground lines running parallel with signal lines effectively shield signals on boards. Filtering can reduce sharp rise and fall times and reduce radiation by wave shaping since more sinusoidal waves have fewer harmonics than square waves. Of course, filters require additional capacitors, resistors, or inductors, raising the cost. All of these techniques are useful to varying extents.
Frequency Modulation - Spread Spectrum
A newer technique to reduce EMI is to vary or modulate the frequency of clocks in the PC. This technique known as spread spectrum, since the frequency spectrum of the clock is spread out over a wider range of frequencies. FIG. 1 shows a graph of radiation intensity as a function of frequency for an un-modulated clock signal. A sharp spike occurs at a harmonic of the clock's frequency, 40 MHz. Since the clock constantly operates at the rated frequency, all of the energy of the radiation appears in a narrow spike, which has a large amplitude. The spike has an amplitude over the EMI limit set by the FCC. The high intensity of the spike can cause interference in a receiver.
FIG. 2 is a graph of radiation intensity as a function of frequency generated by a modulated clock. The clock's frequency is not constant, but is varied with time over a range of +5% to -5% of the rated frequency. Thus the clock operates at 40 MHz for a period of time, but also operates at other frequencies between 38 MHz and at 42 MHz at other times. Such a clock can be generated by slowly changing the frequency from 38 MHz to 42 MHz and then slowly reducing the frequency back to 38 MHz. A voltage-controlled oscillator (VCO) can be used with the input voltage being slewed back and forth between voltages that generate 38 MHz and 42 MHz oscillations.
Since the modulated clock spends only part of the time at 40 MHz, the intensity of the radiation, averaged over a relatively long time, is reduced. The total energy of the radiation at all frequencies is about the same as for the un-modulated clock of FIG. 1, but the intensity at any particular frequency is greatly reduced. Interference at any one frequency is reduced since receivers generally are tuned to a particular frequency (even FM receivers are tuned to a relatively small range of frequencies).
Thus modulating the clock's frequency reduces the maximum intensity of radiation at any one frequency, although the energy radiated at all frequencies is not reduced. This has the practical effect of reducing interference for receivers tuned to a fixed frequency.
The clock's frequency must not change too rapidly. Rapid variations in clock frequency can cause set-up/hold-time problems in logic circuits, and in some cases upset phase-locked loops (PLL's) driven by the modulated clock. These PLL's can lose the phase lock and produce erratic outputs. Thus the frequency is modulated slowly. The clock's frequency must not change too slowly, to avoid losing the benefit of EMI reduction.
Graphics controllers in particular have many clocks derived from the input graphics clock. For instance, for SVGA resolution mode a basic clock is multiplied and divided to generate a 40 MHz pixel clock, a 37 KHz HSYNC clock, and a 60 Hz VSYNC clock, and perhaps a 5 MHz character clock. Different resolutions can require that the clock multiplier and divisors be changed to produce signals with the desired timing for that selected resolution.
Phase-locked loops (PLL's) generate a clock by comparing the phase of an input clock to the phase of a generated clock, which is fed back to the phase comparator. The output of the phase comparator is filtered and then input to a voltage-controlled oscillator (VCO). The VCO varies the frequency of the generated clock as the filtered voltage from the phase comparator varies.
The frequency of the generated clock from the VCO does not have to be the same as the frequency of the input clock. The input clock can be divided by a counter to reduce the frequency of the generated clock (clock divisor), while the generated clock fed back to the phase comparator can be divided to increase the frequency of the generated clock (clock multiplier).
These changeable divisors and multipliers can delay phase comparison by many clock periods, resulting in added delays until a modulation in the clock frequency is responded to. For example, a divisor or multiplier of 16 causes the phase comparison to be delayed up to 16 clock periods. The modulated frequency of the PLL will not change until these delayed phase comparisons are made. Normally it takes three to four phase comparisons (depending on the PLL's open loop gain) before the output frequency settles to within 90% of the newly-set frequency. This results in difficulties in finely controlling the modulation, and inaccuracy in the amount of modulation.
Typically the loop filter values in these PLL's are made large to provide low jitter with a stable reference clock. When this reference clock is purposely modulated, the PLL is no longer operating with a stable reference as it was designed for. This can upset the PLL and introduce more jitter than anticipated.
Long Sweep Period of Modulation--FIG. 3
FIG. 3 is a graph of a modulated clock's frequency as a function of time over a few sweep periods. The clock's nominal frequency is 40 MHz. The clock is modulated by +/-5%, from 38 MHz to 42 MHz. The clock's frequency is swept from minimum to maximum frequencies over one or two thousand clock periods so that adjacent clock pulses have a very small variation. A 40 MHz clock with a 25 nanosecond (ns) period is varied from 26.25 ns to 23.75 ns over a sweep period, a variation of +/-1.25 ns. A 37 KHz sweep rate has a sweep period of 27 micro-seconds (.mu.s). A sweep period is 27 .mu.s / 25 ns or 1081 clock periods. The cycle-to-cycle period variation for two adjacent clock periods is thus 5 ns / 1081 or 4.62 pico-seconds (ps). This small cycle-to-cycle variation is needed to prevent PLL's from losing their phase lock. The sweep frequency is typically 15 to 50 KHz.
A related application for "EMI Reduction for a Flat-Panel Display Controller Using Horizontal-Line-Based Spread Spectrum", U.S. Ser. No. 08/701,814, now U.S. Pat. No. 5,757,338, discloses a spread-spectrum PLL that adjusts the feedback divisor. The modulation rate is synchronized with the horizontal refresh rate of the display to eliminate visible distortions.
Intentional Modulation Disturbs PLL Frequency-Lock
While prior-art modulated clock generators exist, often the stability of the generated clock is compromised when an intentional modulation is introduced. Introducing modulation into a PLL disturbs the frequency-lock and stability of the PLL. Often the amount of modulation must be reduced to maintain frequency-lock. Reducing the amount of modulation is undesirable since the amount of EMI reduction is curtailed.
What is desired is a modulated clock-generator circuit. A more stable clock generator is desired for generating modulated clocks. A PLL-based clock generator that locks in the output frequency even though the output frequency is modulated is desirable. A circuit that more effectively isolates the modulation from the frequency-lock is desired.